`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Andrew Gallasch
// 
// Create Date:    17:08:37 10/21/2013 
// Design Name: 
// Module Name:    math 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module math(
	 input clk,
    input reset,
    input enable,
    input [3:0] address,
    input [31:0] dataIn,
    output reg [31:0] dataOut,
    input write,
    output done,
    output interrupt
    );
	 
	 assign done = 1;
	 assign interrupt = 0;
	 
	 // address usage
	 localparam a_mult_in_1		= 0;
	 localparam a_mult_in_2		= 1;
	 localparam a_mult_out_lo	= 2;
	 localparam a_mult_out_hi	= 3;
	 
	 localparam a_random			= 4;
	 
	 reg [31:0] mult_in_1;
	 reg [31:0] mult_in_2;
	 wire [31:0] mult_out_lo;
	 wire [31:0] mult_out_hi;
		
		reg [31:0] prn;
		
		always @ ( posedge clk )
		begin
			if( write & enable )
			begin
				case( address )
					a_mult_in_1	: mult_in_1 <= dataIn;
					a_mult_in_2	: mult_in_2 <= dataIn;
					a_random		: prn <= dataIn;
				endcase
			end
			else if( ~write & enable )
			begin
				case( address )
					a_mult_out_lo : dataOut <= mult_out_lo;
					a_mult_out_hi : dataOut <= mult_out_hi;
				endcase
			end
		end
		
		assign {mult_out_hi,mult_out_lo} = mult_in_1 * mult_in_2;
		
endmodule
